1. Field of the Invention
The present invention relates to a thin film transistor (TFT) liquid crystal display (LCD) device and more particularly, to a TFT LCD device having a pixel electrode and a counter electrode so configured that an electric field having a horizontal component parallel to the surface of a back substrate is generated in a liquid crystal cell.
2. Description of the Related Art
In general, a TFT LCD device comprises a plurality of unit pixels and thin film transistors respectively corresponding to the unit pixels. Due to such a construction, it can realize a fast responding property, a high picture quality comparable to cathode ray tubes (CRTs), and an enlargement in scale of screen.
At an early stage of the development of such TFT LCD devices, a TN (Twisted Nematic) mode or STN (Super Twisted Nematic) mode has been proposed, in which an electric field perpendicular to the surface of a back substrate is applied to liquid crystal cells. However, TN or STN mode LCD devices have a drawback of a poor viewing angle property. In order to overcome this drawback, an in plane switching (IPS) mode LCD device has been proposed.
In this IPS mode liquid crystal display device, an electric field parallel to the surface of the back substrate is applied to liquid crystal cells. In order to generate such a parallel electric field, a pixel electrode and a counter electrode are arranged in parallel to each other on the back substrate. In this IPS mode LCD device, a viewing angle property can be improved. However, the in plane switching mode LCD device, in which the pixel electrodes and counter electrodes are made of an opaque conductive material, exhibits a low aperture ratio and a degraded transmittance. In order to solve this problem, a fringe field switching mode LCD device has also been proposed (Korean Patent Application No. 98-9243).
The above-mentioned fringe field mode LCD device is illustrated in FIG. 1. FIG. 1 is a plan view illustrating a conventional fringe field mode LCD device manufactured according to the conventional method.
As shown in FIG. 1, in the fringe field mode LCD device a plurality of unit pixels are defined by gate bus lines 2 and data bus lines 4 which are arranged in a matrix form on a back substrate 1. Further, a thin film transistor is disposed in the vicinity of an intersection where one gate bus line 2 and one data bus line 4 cross each other.
In each unit pixel, a counter electrode 5 is formed in the shape of a rectangular plate. The counter electrode 5 is made of a transparent conductive material and is connected to storage capacitor line 7 so as to receive common signals continuously. The storage capacitor line 7 has a first storage capacitor 7a extending in parallel to the gate bus line 2, and a second storage capacitor 7b extending from the first storage capacitor 7a in parallel to the data bus line 4 so that it may be interposed between the counter electrode 5 and the data bus line 4. The first storage capacitor 7a is electrically in contact with the counter electrode 5 whereas the second storage capacitor 7b is electrically insulated from the data bus line 4.
Also in each unit pixel, a pixel electrode 9 is also provided, which is made of a transparent conductive material. The pixel electrode 9 overlaps partially with the counter electrode 5, and is insulated from the counter electrode 5 by a gate insulating film (not shown). The pixel electrode 9 has a plurality of comb-shaped electrode portions 9a, and an electrode bar 9b for connecting respective end of the comb-shaped electrode portions 9a together. The comb-shaped electrode portions 9a are uniformly spaced from one another.
The electrode bar 9b is in contact with a drain electrode of the thin film transistor.
Since both the pixel electrode 5 and the counter electrode 9 are made of a transparent conductive material, high aperture ratio can be realized.
Meanwhile, although not shown, a front substrate is disposed opposite to the back substrate 1. The spacing between the front substrate and back substrate 1 is greater than the spacing between the counter electrode 5 and the pixel electrode 9.
Now, the operation of the fringe field mode LCD device having the above construction will be described.
When a voltage is exerted between the counter electrode 5 and the pixel electrode 9, a fringe field is produced in the liquid cell. Here, since the spacing between the front substrate and back substrate 1 is set to be greater than the spacing between the counter electrode 5 and the pixel electrode 9, a fringe field having a vertical component is generated over the entire upper surface of two electrodes, that is, the counter electrode 5 and the pixel electrode 9. Therefore, liquid crystal molecules over the two electrodes are activated. Thus, a high transmittance is achieved.
A conventional method for manufacturing the fringe field mode LCD device operating as above will be described referring to FIG. 2. FIG. 2 is a cross sectional view illustrating the conventional method for manufacturing the fringe field mode LCD device.
A transparent conductive layer is formed on a back substrate 10, and so patterned according to a first photolithography process that a counter electrode 11 is formed.
A metal layer for a gate bus line is formed on the back substrate 10 where the counter electrode 11 has been formed. Then, though not shown, a gate bus line, a common electrode line and a gate pad are simultaneously formed by a second photolithography process. Here, the gate bus line extends in one direction. The common electrode line is in contact with the counter electrode 11, and the gate pad is located at the edge of the back substrate 10.
A gate insulating layer 12, an amorphous silicon layer for a channel (not shown) and a doped semiconductor layer for an ohmic contact (not shown) are sequentially formed on the back substrate 10 where the gate bus line and the like have been formed. The doped semiconductor layer and amorphous silicon layer are so patterned according to a third photolithography process that a thin film transistor area is defined.
A metal layer for a data bus line is formed on the back substrate 10 where the thin film transistor area has defined. Then, a source electrode, a drain electrode, a data bus line and a data pad, which are not shown in the figure, are formed according to a fourth photolithography process. Here, the source electrode and the drain electrode are formed in the thin film transistor area. The data bus line is arranged to cross the gate bus line, and the data pad overlaps partially with the gate pad.
A protecting layer 13 is formed on the back substrate 10 where the source electrode and so on have been formed. Then, the protecting layer is so patterned according to the fifth photolithography process that a part of the drain electrode, the data pad and the gate pad are exposed.
Finally, a transparent conductive layer is formed so as to contact with the exposed portion of the drain electrode, the data pad and the gate pad on the protecting layer 13. Then, according to a sixth photolithography process the transparent conductive layer is so patterned that a comb-shaped pixel electrode 14 is formed.
In FIG. 2, the reference number 15 represents a back orientation film disposed on the pixel electrode 14 and protecting layer 13, the reference number 20 represents a front substrate opposite to the back substrate 10, the reference number 21 represents a front orientation film disposed on the back surface of the front substrate 20, the reference number 22 represents liquid crystals filled between the two substrates 10 and 20, and the reference characters E1 and E2 represent fringe fields generated between the counter electrode 11 and the pixel electrode 14, respectively.
However, each of the above 6 photolithography processes involves many sub-processes, such as a resist coating process, an exposing process, a developing process, an etching process, a resist removing process and the like. Further, it is required to prepare a different photo mask for every photolithography process. Therefore, in order to reduce the manufacturing costs while increasing the production yield, there is a necessity for reducing the number of the photolithography processes.
Therefore, an object of the invention is to provide a method for manufacturing a thin film transistor LCD device in which the number of photolithography processes used is reduced in order to solve the above-mentioned problem involved in the related art.
A present method for manufacturing a thin film transistor LCD device having a back substrate, a front substrate opposed to said back substrate, a liquid crystal cell interposed between the front and back substrates, a pixel electrode formed on the back substrate, a counter electrode formed on the back substrate and adapted to cooperate with the pixel electrode to generate an electric field having a horizontal component parallel to a surface of the back substrate, and a thin film transistor including a gate electrode, a source electrode, and a drain electrode, the thin film transistor serving to apply an image signal voltage between said pixel electrode and said counter electrode, comprising the steps of:
a transparent conductive layer for the counter electrode and a metal layer for the gate bus line on the back substrate sequentially deposed. Thereafter, a first photoresist layer is formed on said deposited metal layer for the gate bus line; Thereafter, said first photoresist layer is so exposed to a scanning light that the portion of the first photoresist layer disposed over a counter electrode region for forming said counter electrode is partially lightened; Thereafter, said first photoresist layer is so patterned that an area of the metal layer for the gate bus line lying under the partially lightened portion of the first photoresist layer is not exposed; Thereafter, said metal layer for the gate bus line is so patterned by using said patterned first photoresist layer as a barrier layer that said counter electrode region and a gate bus line region may are defined; Thereafter, said transparent conductive layer for the counter electrode is so patterned by using said patterned metal layer as a barrier layer that said counter electrode is formed; Thereafter, said metal layer for the gate bus line is so patterned by using said patterned first photoresist layer as a barrier layer that said gate bus line is formed; Thereafter, the thin film transistor is formed on said back substrate where said gate bus line has been formed; Thereafter, a protecting layer is formed on said back substrate where said thin film transistor has been formed; Thereafter, said protecting layer is so patterned that a part of the drain electrode included in said thin film transistor is exposed; Thereafter, a transparent conductive layer for the pixel electrode is formed on said back substrate where said drain electrode has been exposed; and said transparent conductive layer for the pixel electrode is so patterned that said pixel electrode is formed.
At the step of exposing the first photoresist layer to the scanning light, the first photoresist layer over the counter electrode is partially exposed to a scanning light by using a first photo mask a portion of which corresponding to the area of said first photoresist layer located over the counter electrode region has opening parts and closed parts arranged in a lattice form.
Further, in order to form a gate pad and a data pad simultaneously, the step of exposing said photoresist layer to the scanning light may be carried out by exposing said first photoresist layer to the scanning light so that a data pad region and a gate pad region for forming a data pad and a gate pad respectively may be defined at the edges of the back substrate; the step of patterning said metal layer for the gate bus line may be carried out by patterning said metal layer so that the data pad and the gate pad may be formed simultaneously with the gate bus line; the step of patterning said protecting layer may be carried out by patterning the protecting layer so that the data pad and the gate pad may be exposed; and the step of forming said transparent conductive layer for the pixel electrode comprises may be carried out by forming the transparent conductive layer for the pixel electrode so as to contact with the exposed data pad and gate pad.
Further, in order to reduce the number of photolithography processes used, the step of forming the thin film transistor may be carried out by the following procedures.
A gate insulating layer, an amorphous silicon layer for a channel, a doped semiconductor layer for an ohmic contact, and a metal layer for source/drain electrodes are sequentially deposed on the back substrate where said counter electrode and said gate bus line have been formed; Thereafter, a second photoresist layer is formed on said deposited metal layer for source/drain electrodes; Thereafter, said second photoresist layer is so exposed to a scanning light that the portion of said second photoresist layer lying over an area of the metal layer for source/drain electrodes defined between a source electrode region for forming the source electrode and a drain electrode region for forming the drain electrode is partially lightened; Thereafter, said second photoresist layer is so patterned that the area of the metal layer for source/drain electrodes lying under the partially lightened portion of said second photoresist layer is not exposed; Thereafter, said metal layer for source/drain electrodes is so patterned by using said patterned second photoresist layer as a barrier layer that said source electrode region and said drain electrode region are defined; Thereafter, said doped semiconductor layer for the ohmic contact is patterned by using said patterned metal layer as a barrier layer that an ohmic contact region for forming ohmic contacts for the source electrode and the drain electrode are defined; Thereafter, said amorphous silicon layer for the channel is so patterned by using said patterned doped semiconductor as a barrier layer that a channel of the thin film transistor is formed; Thereafter, said metal layer for source/drain electrodes is so patterned by using said patterned second photoresist layer as a barrier layer that the source electrode and drain electrode are formed; and said doped semiconductor layer for the ohmic contact is so patterned by using said source electrode and the drain electrode as barrier layers that the ohmic contacts of the source electrode and the drain electrode are formed.